1. Field of the Invention
The present invention relates to a method for reproducing a printed circuit board (PCB) for semiconductor packages, and more particularly to a matrix type PCB for semiconductor packages having a structure including a plurality of PCB units arranged in a matrix array having at least two rows in such a fashion that the mold runner gates of adjacent PCB units respectively arranged in adjacent rows while being arranged in the same column communicate with each other by an integrate mold runner, thereby being capable of allowing an increased number of PCB units to be simultaneously processed in each process involved in the fabrication of semiconductor packages, so that a great improvement in productivity is achieved.
2. Description of the Prior Art
Generally, a PCB is a circuit board adapted to transmit electrical signals from a semiconductor chip mounted thereon to an external unit and from the external unit to the semiconductor chip. Such a PCB is fabricated by laminating conductive thin films over upper and lower surfaces of a resin substrate made of a glass fiber reinforced thermosetting resin composite, patterning the conductive thin films in accordance with well-known photolithography processes, thereby forming circuit patterns on the upper and lower surfaces of the resin substrate, electrically connecting those circuit patterns to each other by via holes, and coating solder masks, made of a polymer resin, on the upper and lower surfaces of the resin substrate at desired regions, respectively.
The PCB having the above mentioned structure is called a xe2x80x9csingle-layer PCBxe2x80x9d. Recently, a multi-layer PCB has been proposed which is formed by laminating a plurality of single-layer PCB structures, each having a resin substrate and a pair of conductive circuit patterns, to form a multi-layer PCB structure. In such a multi-layer PCB structure, adjacent conductive circuits of adjacent layers are electrically connected by conductive via holes.
Referring to FIG. 1, a conventional PCB strip having the above mentioned structure is schematically illustrated.
As shown in FIG. 1, the PCB strip, which is denoted by the reference numeral 10xe2x80x2, includes a resin substrate 6xe2x80x2 having a rectangular strip shape. A plurality of conductive circuit patterns (not shown) are formed on each of upper and lower surfaces of the resin substrate 6xe2x80x2. Solder masks 5xe2x80x2 are also formed on the upper and lower surfaces of the resin substrate 6xe2x80x2, respectively, in order to protect the conductive circuit patterns formed on the upper and lower surface of the resin substrate 6xe2x80x2 from the surrounding environment while preventing those conductive circuit patterns from being short-circuited. A plurality of mold runner gates 2xe2x80x2 are formed on the upper surface of the resin substrate 6xe2x80x2. Each mold runner gate 2xe2x80x2 is arranged at one corner of a region corresponding to one of PCB units 10axe2x80x2 longitudinally aligned with one another along the PCB strip in the form of a strip. Each mold runner gate 2xe2x80x2 is plated with gold (Au) or palladium and adapted to guide a melted encapsulating resin of high temperature and high pressure to a resin encapsulation region defined on an associated one of the PCB units 10axe2x80x2. The resin encapsulation region of each PCB unit 10axe2x80x2 is defined by a resin encapsulation line 4xe2x80x2. The melted encapsulating resin is introduced into the resin encapsulation region of each PCB units 10axe2x80x2 through an associated one of the mold runner gates 2xe2x80x2, and then cured, thereby forming a resin encapsulate encapsulating a semiconductor chip mounted on the PCB unit 10axe2x80x2 along with bonding wires. After the formation of the resin encapsulates, the surplus encapsulating resin cured in each mold runner gate 2xe2x80x2 serving as a resin introduction passage is subjected to a degating or deculling process so that it is removed. Since the gold or palladium coated over the mold runner gates 2xe2x80x2 exhibits a bonding force to the encapsulating resin considerably lower than the bonding force to the resin substrate or the solder mask, the surplus encapsulating resin cured in each mold runner gate 2xe2x80x2 can be easily removed without causing the solder mask and circuit patterns to be damaged.
For the formation of the resin encapsulates, an upper mold and a lower mold (not shown) are used which are engaged with each other. At the region defined by the resin encapsulation line 4xe2x80x2 in each PCB unit 10axe2x80x2, an associated one of cavities defined in the upper mold is arranged. The melted encapsulating resin fills each cavity, and is then cured, thereby forming a resin encapsulate. In FIG. 1, the reference numeral 3xe2x80x2 denotes package unit singulation lines along which the PCB strip 10xe2x80x2 is cut into individual semiconductor packages respectively corresponding to the PCB units after the resin encapsulate formation so that those semiconductor packages are separated from one another.
A plurality of spaced pin holes 7xe2x80x2 are formed at each longitudinal edge of the PCB strip 10xe2x80x2 in order to allow an easy feeding of the PCB strip 10xe2x80x2 between adjacent processes.
The conductive circuit patterns of adjacent PCB units 10axe2x80x2 in the PCB strip 10xe2x80x2 are electrically connected. Accordingly, the electroplating process for the conductive circuit patterns of all PCB units 10axe2x80x2 can be conducted in a single pass. After the completion of the electroplating process, slots 1xe2x80x2 are perforated through respective portions of the PCB strip 10xe2x80x2 where the conductive circuit patterns of adjacent PCB units 10axe2x80x2 are electrically connected, thereby causing those conductive circuit patterns to be disconnected. As a result, it is possible to easily conduct an open/short circuit test for each PCB unit 10axe2x80x2. It is also possible to prevent the PCB strip 10xe2x80x2 from being bent due to a thermal expansion coefficient difference between the resin substrate 6xe2x80x2 and the circuit patterns when being subjected to high temperature processes conducted in the fabrication of semiconductor packages.
However, the above mentioned conventional PCB strip 10xe2x80x2 has a problem in that there is a great limitation on the number of semiconductor packages fabricated from one PCB strip. For instance, only seven semiconductor packages can be fabricated from the PCB strip shown in FIG. 1. Although active attempts have been made in a variety of fields associated with the fabrication of semiconductor packages to reduce the manufacturing costs, there is a limitation on the reduction of manufacturing costs insofar as the PCB strip 10xe2x80x2 having the above mentioned structure is used. The above mentioned PCB strip structure also involves a problem of a low productivity in that there is a great limitation on the number of PCB units processed per process in the fabrication of semiconductor packages.
An object of the present invention is to provide a matrix type PCB for semiconductor packages having a structure capable of allowing an increased number of PCB units to be simultaneously processed in each process involved in the fabrication of semiconductor packages, thereby achieving a great improvement in productivity.
A second object of the invention is to provide a matrix type PCB for semiconductor packages having a structure capable of allowing an increased number of PCB units to be simultaneously molded in a resin encapsulate molding process, thereby achieving a great improvement in the efficiency of the resin encapsulate molding process.
A third object of the invention is to provide a matrix type PCB for semiconductor packages having a structure capable of easily and reliably removing surplus encapsulating resin materials cured in mold runner gates and integrate mold runners in accordance with a degating and/or deculling process without surface damage to the PCB.
A fourth object of the invention is to provide a matrix type PCB for semiconductor packages having a structure capable of allowing an easy open/short circuit test for individual PCBs.
In accordance with the present invention, the first and second objects are accomplished by providing a matrix type printed circuit board for semiconductor packages comprising: a resin substrate having a rectangular shape provided with two parallel longer edges and two parallel shorter edges; a plurality of printed circuit board (PCB) units formed on at least one surface of the resin substrate and arranged in a matrix array having at least two rows, each of the PCB units having a semiconductor chip mounting region at a central portion thereof; a plurality of first mold runner gates each formed at one corner of an associated one of the PCB units included in a first one of the at least two rows arranged adjacent to a first one of the longer edges of the resin substrate, the one corner being arranged adjacent to the first longer edge of the resin substrate; a plurality of second mold runner gates each formed at one corner of an associated one of the PCB units included in a second one of the at least two rows arranged adjacent to the first-row PCB units, the one corner of each PCB unit included in the second row being arranged nearest to the first mold runner gate of an associated one of the PCB units arranged in the first row and in the same column as the second-row PCB unit; and a plurality of first integrate mold runners each extending straight between the first and second mold runner gates of adjacent ones of the PCB units respectively arranged in the first and second rows while being arranged in the same column.
In accordance with one aspect of the present invention for accomplishing the third object, the matrix type printed circuit board, which has a configuration capable of accomplishing the first and second objects, has a configuration including a through hole formed at each of the second mold runner gates and provided with a plated inner wall surface or a deculling dummy pattern formed at each of the first integrate mold runners.
In accordance with another aspect of the present invention for accomplishing the fourth object, the matrix type printed circuit board, which has a configuration capable of accomplishing the first and second objects, has a configuration including a slit perforated through a solder mask opening region where a conductive bus line is arranged while extending in parallel to an associated one of the first integrate mold runners, the slit serving to electrically disconnect conductive traces, extending across the conductive bus line, from one another.